Forum Discussion
Altera_Forum
Honored Contributor
12 years agoDid you get an answer for this one?
I find that even if you add the Verilog Include files to the "Synthesis Files" list, and set Type="Verilog Include", the invocation of quartus_map to figure out the top level pins is not passed the corresponding -I argument. We worked around this by making a sym link from module current directory to the verilog include file, and then checking in the sym links to source code repository (git). The only problem is that this then breaks on Windows :-(