MShai9
New Contributor
New ContributorGetting an error :object "led" on left-hand side of assignment must have a variable data type
module test (clk,led);
input clk;
output led;
reg [7:0] counter;
always@(posedge clk) begin
if (counter < 100) counter <= counter +1;
else counter <= 0;
end
always @ (counter) begin
if (counter>0) led = 1;
else if (counter<20) led = 1;
else led = 0;
end
endmodule
trying to make sure that the value of led turns 1 only when the value of counter varies from 1 to 20. I want led to be zero when counter is zero. any workaround this or am i doing something wrong?
