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Vhdl and java are different things and converting from one to the other is not trivial. You need to understand digital logic to convert to vhdl
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I have a certain java file, when i run that file I get a window where i have to select component and type of component weather it is behavioral or structural component,and i have to also select states and transitions if it is behavioral and then i have to export it as vhdl after exporting it should generate .vhd file.
for example the below generated file is for behavioral(fsm) .vhd file which was generated using python but i have to do in java.
-- fsm for VHDL export by SpecScribe
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fsm is
PORT (
global_clk : IN std_logic;
reset : IN std_logic;
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic);
END fsm;
ARCHITECTURE fsm_A OF fsm IS
type fsmstatetype is ( state1, state2, state3);
BEGIN
fsm_P : PROCESS (reset, global_clk)
VARIABLE testvariable : std_logic := '0';
VARIABLE fsmstate : fsmstatetype:= state1;
BEGIN
IF (reset = '1') THEN
testvariable:= '0';
fsmstate := state1;
ELSIF (global_clk'event and global_clk = '1') THEN
CASE fsmstate IS
WHEN state1 =>
IF (a='1') THEN and not (b='1') THEN
testvariable := '1';
fsmstate := state2;
ELSE
fsmstate := state1;
END IF;
WHEN state2 =>
IF (a='1') THEN and (b='1') THEN
testvariable := '0';
fsmstate := state3;
ELSE
fsmstate := state2;
END IF;
WHEN state3 =>
IF not (a='1') THEN and not (b='1') THEN
testvariable := '1';
fsmstate := state1;
ELSE
fsmstate := state3;
END IF;
END CASE;
END IF;
c <= testvariable;
END PROCESS;
END fsm_A;
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