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Altera_Forum's avatar
Altera_Forum
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12 years ago

Generic Priority Encoder

Is there a better way to generate a generic priority encoder without IF/ELSEIF? I need the parameterize my encoder (before synthesis), without recoding manually every time. I have manually coded up a fixed priority encoder, and clearly IF/ELSEIF is less optimal than using CASE statement. But I haven't been able to keep it generic without using IF/ELSEIF. It needs to be minimal logic layers.

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I couldn't find it in my altera_mf_components.vhd file, but I instantiated it anyway and it seems to work. Maybe it's been moved to another file?

    --- Quote End ---

    The VHDL component definition is in quartus\libraries\vhdl\altera_mf\altera_mf_components.vhd, for all Quartus versions since V7 at least.

    Altera is using it in many arithmetic MegaFunctions internally, for some reason, they didn't document the function.

    component altpriority_encoder
       generic (
          lsb_priority   :  string := "NO";
          pipeline :  natural := 0;
          width :  natural;
          widthad  :  natural;
          lpm_hint :  string := "UNUSED";
          lpm_type :  string := "altpriority_encoder"
       );
       port(
          aclr  :  in std_logic := '0';
          clk_en   :  in std_logic := '1';
          clock :  in std_logic := '0';
          data  :  in std_logic_vector(width-1 downto 0);
          q  :  out std_logic_vector(widthad-1 downto 0);
          zero  :  out std_logic
       );
    end component;

    --- Quote Start ---

    My design ideally would be able to run in excess of 333 MHz which might not be realistic.

    --- Quote End ---

    With how many pipeline (register) levels? Which FPGA family? You have already 2 register levels (in- and output registers) in your example code.
  • Altera_Forum's avatar
    Altera_Forum
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    Is this function not supported in ModelSim?? When I compile the altera_mf, I don't see it in the library. Any thoughts?

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Is this function not supported in ModelSim?? When I compile the altera_mf, I don't see it in the library. Any thoughts?

    --- Quote End ---

    I found it here:

    \altera\quartus\libraries\vhdl\altera_mf
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Is this function not supported in ModelSim?? When I compile the altera_mf, I don't see it in the library. Any thoughts?

    --- Quote End ---

    There is probably no functional simulation model. altpriority_encoder is used internally in the synthesis of several arithmetic MegaFunctions, but apperently not in the respective simulation models.

    But what's the point of simulating altpriority_encoder? For the functional simulation you can replace it by a simple behavioral model as suggested previously in this thread. If you are interested in timing behaviour, you'll refer to gate level simulation.
  • Altera_Forum's avatar
    Altera_Forum
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    Any MegaFunction should have an associated model. The priority encoder is simple enough to generate my own behavioral model, but I shouldn't have to if it's an Altera IP. I'm also not simulating just the encoder by itself, it's of course a part of a much larger system model, and it will be used many times all with different input parameters. I don't really want to get involved in the gate level stuff until I get a functional model working, it just slows down the work flow. Thanks.