--- Quote Start ---
I couldn't find it in my altera_mf_components.vhd file, but I instantiated it anyway and it seems to work. Maybe it's been moved to another file?
--- Quote End ---
The VHDL component definition is in quartus\libraries\vhdl\altera_mf\altera_mf_components.vhd, for all Quartus versions since V7 at least.
Altera is using it in many arithmetic MegaFunctions internally, for some reason, they didn't document the function.
component altpriority_encoder
generic (
lsb_priority : string := "NO";
pipeline : natural := 0;
width : natural;
widthad : natural;
lpm_hint : string := "UNUSED";
lpm_type : string := "altpriority_encoder"
);
port(
aclr : in std_logic := '0';
clk_en : in std_logic := '1';
clock : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(widthad-1 downto 0);
zero : out std_logic
);
end component;
--- Quote Start ---
My design ideally would be able to run in excess of 333 MHz which might not be realistic.
--- Quote End ---
With how many pipeline (register) levels? Which FPGA family? You have already 2 register levels (in- and output registers) in your example code.