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We think you need to write a simulation.
Altera provides a verification IP suite. You should use that suite to confirm your code simulates correctly.
You comment above that you are new to VHDL, so here is a piece of advice for you to follow; Writing a simulation should be an integral part of your code development, not an afterthought.
Cheers,
Dave
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Well, I need to build something to be able to simulate it and then consequently to verify it. Now that I have built it, I can simulate it.
I have noticed though, based on reading most of the threads on this sub-forum for VHDL that community on this forum/site is not as warm and welcoming as is on forums for mbed, avr or arduino where people discuss, help and teach/learn from each other. Here it is more business-like which does not really welcome beginners or people wanting to learn something....it is strange - because if it were different more people would probably be eager to learn and use FPGA/CPLDs.
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