Generic driver to rest of the system communication - advice needed?

--- Quote Start ---

I have looked at the Avalon bus specification for memory mapped slaves and devised a similar protocol ...

Didn't have time to do simulation yet - holidays & such.

What do you all think?

--- Quote End ---

We think you need to write a simulation.

Altera provides a verification IP suite. You should use that suite to confirm your code simulates correctly.

You comment above that you are new to VHDL, so here is a piece of advice for you to follow; Writing a simulation should be an integral part of your code development, not an afterthought.

Cheers,

Dave