Generic driver to rest of the system communication - advice needed?

Thanks for your reply.

There is no code nor timing diagrams since I wanted to describe my idea first in an human time-efficient manner which is by using words.

Developing the solution to produce code and timing diagrams would take some time after which someone can provide better or more efficient protocol type, which is also simple to implement but I didn't even know it exists.

Are there any "design patterns" or "best practices" books or papers for always repeating codes and/or glue logic such as this? Because I am sure that in most more complex FPGA solutions you have bunch of "modules" communicating with each other (sending, reading, waiting for completion of some task, etc). It is very hard to find something online as opposed to software where this is common.

Request/acknowledge type interface would work as:

1. Byte data put on input vector of FT245 driver. FT245 driver "data_sent" bit is low.

2. Request to write put high.

3. FT245 driver goes to next state and performs sending sequence.

4. FT245 driver goes to state upon completion of sending sequence and puts data_sent bit high.

5. Requester waits for data_sent to become high. When this happens, puts request to write to low and puts ACK bit to FT245 as high.

6. FT245 driver puts "data_sent" bit back to low and goes to idle state.

As for data rate:

@ 50Mhz clock every clock is at 20ns. Write pulse to FT245 chip is at minimum 50ns (= 3 clock cycles = 60ns). Read pulse is also 50ns (= 3 clock cycles = 60ns). I would loose about 3-4 clocks on this "communication protocol" making my write speed about 7 clock cycles (140ns) for 1 byte. This is 6.811MB/s which is well over the USB 2.0 data rate limit. so It is OK. however I would definetly like to learn more about more efficient implementations to know for the future!