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Altera_Forum's avatar
Altera_Forum
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16 years ago

generating a pulse pattern in VHDL

Hi, I am trying to generate a pulse using DE2 developement board. I need to set the output high and create a delay and low again - again a different delay and high again. I did this using a co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

What are you trying to achieve? A test signal generator? Multple phase shifted clocks can be a solution. But you have to care for correct synchronisation when crossing the clock domain boundaries.