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Altera_Forum's avatar
Altera_Forum
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16 years ago

generating a pulse pattern in VHDL

Hi, I am trying to generate a pulse using DE2 developement board. I need to set the output high and create a delay and low again - again a different delay and high again. I did this using a co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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inefficient:- methods like using counters make errors due to gate delays.

In fact, what I am trying to do is to create the signals as in attached image.

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But gate delays are innevitable when using a clock, down to a minimum period of 1 clock. If you're having problems with gate delays, increase the clock frequency.