Altera_ForumHonored Contributor16 years agogenerating a pulse pattern in VHDL Hi, I am trying to generate a pulse using DE2 developement board. I need to set the output high and create a delay and low again - again a different delay and high again. I did this using a co...Show More
Altera_ForumHonored Contributor16 years agoI don't understand the meaning of ineficient in your post.
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