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Altera_Forum
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16 years ago

generating a pulse pattern in VHDL

Hi, I am trying to generate a pulse using DE2 developement board. I need to set the output high and create a delay and low again - again a different delay and high again. I did this using a co...
Altera_Forum's avatar
Altera_Forum
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16 years ago

counters or state machines can do that readily. Delay units will be in clk periods. You can also use the two clk edges then combine the results allowing you half clk period units.

If you want other delay units unrelated to clk then that technlogy is not available yet in fpgas. For example you can use Tco of registers or combinatorial delays but all are unpredictable.