Generated clock constraint - not a pll or mux clock

Below is my answer to address you question:

1. Given that the clock to be frequency-doubled is "clk_in" and the shift-register clock is "hs_clk", can you provide an example of the generated clock constraint statement for "clk_x2" that would accomplish this?

- You can use the following general format:

create_generated_clock -name clk_x2 -multiply_by 2 [get_pins <output_pin_of_shift_register>]

Note that you should replace "<output_pin_of_shift_register>" with the name of the output pin of your shift-register that is connected to clk_in.

2. Specifically, if "hs_clk" is treated as the source, as you suggest, then is the "multiply_by 2" argument not required since I am not doubling the frequency of "hs_clk"?

- Regarding your second question, if hs_clk is treated as the source clock in your constraint, then you do not need to include a "multiply_by 2" argument because it is already being doubled by the shift-register and XOR gate. The generated clock constraint simply tells Quartus that clk_x2 is derived from hs_clk and has double its frequency.