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tedh4ddv's avatar
tedh4ddv
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Generated clock constraint - not a pll or mux clock

I need to double the frequency of a clock, but the source is not a clock pin, so I am unable to use a PLL. I opted to use a shift-register and exclusive-OR gate, instead. Should the high-speed cloc...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
2 years ago

Can you share your constraint here? What is the constraint specify in the design.

Snippet would be enough


tedh4ddv's avatar
tedh4ddv
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

The following is the constraint I used, but I don't see how Quartus will relate this to the high-speed clock driving the shift-register.

create_generated_clock -name cvbs1_clk_2x -source [get_pins {p0_out|mux0_clock|combout}] -multiply_by 2 [get_pins {ifb_dec|clkx2_1|clk_2x|q}]