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tedh4ddv's avatar
tedh4ddv
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2 years ago

Generated clock constraint - not a pll or mux clock

I need to double the frequency of a clock, but the source is not a clock pin, so I am unable to use a PLL. I opted to use a shift-register and exclusive-OR gate, instead. Should the high-speed cloc...
tedh4ddv's avatar
tedh4ddv
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Given that the clock to be frequency-doubled is "clk_in" and the shift-register clock is "hs_clk", can you provide an example of the generated clock constraint statement for "clk_x2" that would accomplish this? Specifically, if "hs_clk" is treated as the source, as you suggest, then is the "multiply_by 2" argument not required since I am not doubling the frequency of "hs_clk"?