Generated clock constraint - not a pll or mux clock

In this scenario, the constraint's 'SOURCE' should be set to the high-speed clock (hs_clk) driving the shift-register.

This is because the frequency of the high-speed clock (hs_clk) and the number of stages in the shift-register both affect the frequency of the clock that is being multiplied (clk_in). The output frequency (clk_in) will increase when the shift-register and XOR gate are used to double the frequency of hs_clk. The high-speed clock driving the shift-register must therefore be correctly restricted when the clock network is constrained, and the constraints must also take into account the frequency of clk_in that results.