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Altera_Forum's avatar
Altera_Forum
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12 years ago

generate with step other than unit

Hi, I need to write a GENERATE statement, but the step must be different from unit. Something like: gen: for i in 0 to 20 generate temp(i) <= temp(i+4-2) or temp(i+...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

To learn about allowed VHDL constructs I suggest to read a text book or the LRM.

In the present case, these points should be considered:

- the range of sequential for loops as well as generate loops must be constant.

- you can achieve a variable range or a variable step size in sequential for loops by combining it with conditional statements

- this is impossible with generate statements by their nature