Generate VHDL code from VHDL code

I am finally getting the idea about what is supposed to happen and what would be a solution.

I must say I have never made a testbench before, the way to test and verify my code works was with doing little tests with modelsim and try and see what happens when I programm the chip.

A testbench is just a simulationmodel, build to verify what your design does, right? Some automated way to check every possibility?

Since I am not familiar with testbenches, I am not sure if I would need them. Because the design has to do what it has to do and I assume the IP blocks are correct. So that means the only thing that needs to be tested is if the blocks are connected in the right way.

I must really thank you for the advice and options, I think I wouldn't have understand my problem this far without it:)

Who would have thought you could learn so much off a forum