Generate VHDL code from VHDL code

It sounds like you've got a good handle on the trade-offs.

One thing I did not like about Wishbone when I last looked at it, was there was no decent bus functional model (BFM) support needed for creating testbenches (the Wishbone equivalent of Altera's Verification IP suite).

You really need to have a BFM to build components. Sure you can write a BFM and then create your components, however, if you incorrectly interpreted the specification, then you will code that error into both your master and target BFMs. Its usually a little nicer if the BFM is already available.

Cheers,

Dave