Honored Contributor
Honored ContributorI got a great inspiration yesterday when I was reading about AMBA, it sounded so familiar but I didn't know why. Well now I know, the guys before me have been looking into the different interfaces to use and which one was best. So they have decided it was going to be Wishbone with all of their explanations and stuff.
--- Quote Start --- The major issue you face with using Wishbone in Altera tools is that you lose the ability to use Qsys. Qsys is useful in that it creates all the multi-master/multi-slave address-decoding and arbitration logic. Sure you can create it yourself, but Qsys saves you having to. --- Quote End --- I am not sure if I agree on that. I prefer not to rely on any tools used by vendors, if I can do it myself and know EXACTLY what will happen. Since those tools can change, or might not work properly, I cannot do anything about such a thing. But when it's in the program/design I made, I can look for the problem and try to solve it. With using Qsys you would have to find a workaround and know which version they have. Ofcourse when it is all my design, it might have even more problems than Qsys, but at least I would have one standard tool to use for every vendor. That is also why I try to do things without all those vendor specific tools, unless it is really not possible. So in short: there are already a few designs made by hand, but done in a way they are most similiar. Wishbone has been chosen as the interface bus. Every design has a specific FPGA block, uses the wishbone and has some component to work with. User chooses FPGA and component, I know these blocks, put the design together and compile it with the vendor specific tool. User may have the option to say when the design needs to be programmed in the FPGA, or it is done right away if possible. I think thats about it
