Generate VHDL code from VHDL code

This discussion is getting fairly long and complex. I'll just focus on the interface issue for now.

--- Quote Start ---

Supporting Wishbone is the 'only' requirement for now

--- Quote End ---

Who made this requirement?

You need to realize that if you create a component that is Wishbone compliant, that it is not compatible with Altera Qsys and it is not compatible with Xilinx tools. It would however be compatible with Lattice tools (and their Mico32 soft-core processor).

This is why I said that the vendors have already made the interface decision for you. Qsys supports Avalon components, and more recently AXI components.

Lets take something as simple as an on-chip RAM. The Avalon interface and Wishbone interface are very similar, if not identical. However, the naming convention for the entity ports is different, so at a minimum you would want to adhere to the interface standard and name the signals appropriately. For example, an Avalon-MM slave single-port RAM interface is

entity avs_single_port_ram is
  generic (
    AWIDTH : integer := 5;
    BWIDTH : integer := 4;
    DWIDTH : integer := 32
  );
  port (
    -- Reset and clock
    rstN        : in  std_logic;
    clk         : in  std_logic;
    -- Avalon Slave Interface
    avs_read    : in  std_logic;
    avs_write   : in  std_logic;
    avs_addr    : in  std_logic_vector(AWIDTH-1 downto 0);
    avs_byteen  : in  std_logic_vector(BWIDTH-1 downto 0);
    avs_wrdata  : in  std_logic_vector(DWIDTH-1 downto 0);
    avs_rddata  : out std_logic_vector(DWIDTH-1 downto 0);
    avs_rdvalid : out std_logic;
    avs_wait    : out std_logic
  );
end entity;

but the equivalent Wishbone part would have a different prefix, and _i and _o suffices on the signals.

The major issue you face with using Wishbone in Altera tools is that you lose the ability to use Qsys. Qsys is useful in that it creates all the multi-master/multi-slave address-decoding and arbitration logic. Sure you can create it yourself, but Qsys saves you having to.

Since you say you only have half a year to complete this, you first need to write up the "Project Deliverables", i.e., define the minimum set of features you expect to implement. In that same document you should also describe how this code fits into the larger picture, but you need to focus on a subset first, otherwise you will get lost in the complexity.

What you should do next is to write up a document that distills your project goal. Take some of this discussion and use it to fill in details. Put "TODO" where you are missing information. Post it here on the forum, or email it to me directly and I'll read through it. Make sure to include some use-cases of example users and how you expect them to use your code, eg., what is their hardware, how are they supposed to download a new image to their board, etc.

Cheers,

Dave