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Wow I din't think that processor code would be so big. Or maybe I am looking into more than just the processor. I've got the idea I have about a gig or more on just manuals and stuff. I don't know where to start, so I have been looking around in the files. But most feel like they have been created in some way I haven't found yet. I think I have enough to read for about a year or so now?
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This should give you an idea of how "complex" things can become :)
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Ah, but than I believe I am supposed to do those things via Wishbone.
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What do you mean "I believe"? You have either been asked to do it or not. There should be no uncertainty.
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The good thing is, I don't have to design all the files that are going to be used. So I can define what they should look like(as far as it's reasonable ofcourse), which will make it easier to make a more general approach I believe.
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I'm afraid you are not being specific enough. There is no one general approach, there are many many approaches. As I commented earlier, there are many standard buses. If you plan on supporting; AXI, Avalon, and Wishbone, then you will have a lot of work to do.
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I need to invent a good design which will cover a lot of devices, without the need of too much reconfiguring I would assume. So that's also a challange.
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You don't get to invent anything. Altera, Xilinx, and Lattice have already defined the bus protocols their respective tools understand. If you want people using those tools to use your components, then you have to supply the bus interfaces acceptable to those vendors.
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Oh and if it's not possible to use the wishbone, it must also be possible to choose another already designed interface. But thats a thing for the user to choose, so the user can choose another interface if he would like that for some reason.
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No, its not up to the user to decide. The decision has already been made by the FPGA vendor.
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So if I understand the documentation correctly, the configuration files of the FPGA's are put in a fifo somewhere on the board. And read some time when they are told to be reconfigured?
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No. The configuration files are transferred from a network filesystem or flash. The FIFOs are in there to decouple clock domains and implemented data flow control.
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I have just found out the files Quartus standard creates to program your device aren't the only way indeed to programm the device. It is sometimes hard to remember there are more ways to do something, what you have always done some specific way. I must also say it isn't easy for me to walk away from the known path, so I didn't like the other ways to program the device. But it is sure a good thing to know.
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There are indeed multiple methods to configure devices. Not all are easily available. For example, if a user has a board plugged into their PC, it might not be possible to access the JTAG connector. If that same board is using the FPGA as the PCIe interface, then not all FPGAs support being reprogrammed without cycling power of the user PC ...
Cheers,
Dave
Honored Contributor
