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Its a bus protocol, just like Altera's Avalon standard, and the OpenCores Wishbone standard. The AXI standard is an ARM standard.
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Ah that makes sense. So that would mean I would have another layer in my design which I would call FPGA bus. Thats not that bad, but it also means I would have to make the FPGA blocks in a way they can be connected to that bus, right? Or could there be a possibility there already are the blocks to integrate the AXI standard?
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Of course, the user can still be ignorant of the HDL if they are just downloading a pre-compiled image.
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Exactly! Thats what I want, I want to do all the work for the user, so that the user has its compiled image and can just push a button I made in my interface and it will be programmed in it. I am just not aware if it is possible to make such a thing, or if I would have to start quartus for example and let the user push the program button there.
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