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Luckily I only have to support Altera and Xilinx for now, still different vendors, but might make it easier. I can't seem to find the IP blocks of Xilinx(Altera are the asmi blocks you need to use, right?), so I can make sure they have the same in and outputs. If they have it should be simple with configurations, or is it still easier to just change the entity name to the component that needs to be used with another script I was planning to make?
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Yes, at some level you can make the components look identical.
For example, since Altera and Xilinx both support AXI, I would recommend making every component have standard AXI interfaces as much as that seems reasonable. Before jumping into that though, I would first check whether there are good verification tools available for the AXI interface testing, eg., either from Altera or Xilinx, or from ARM.
By standardizing on an interface, you only have to generate a single component, rather than one per vendor.
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Good thing is, the user may not customize the design I created. All he has to do is to tell which components he wants to use and which pins are attached to those. This way the user doesn't even need to know how an FPGA works, as long as he knows how to shoot the program in it(and if it's possible to automate that, the user doesn't have to do that either).
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What does your hardware target look like? There are very few interfaces where the user will just "shoot the program in it". Most FPGA designs need to be configured at power-on. This is especially true of low-cost designs, where you can't afford to have multiple FPGAs on a board.
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I was thinking to arrange the code with at least folders FPGA and Components, maybe I need to think better and more about that also indeed.
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Download the Leon SPARC processor code from Gaisler, look at open cores, etc. See how others deal with it. I expect you would have an area for generic HDL, another for vendor-specific HDL (with wrappers to make it look generic, for use by the generic HDL), and an area for target devices.
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Those hardware blocks like SPI, I2C, SRAM, DRAM, whatever you can think of, can always be implemented the same no matter what the board looks like or what FPGA is used right? Except for the memory components, they can be bigger or smaller of course. Or did I miss more?
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Right. You create parameterized components (that are customized by VHDL generics or Verilog parameters). You might actually have several implementations of similar components. Then under each vendors tool, eg., Altera Qsys, you create a _hw.tcl script to make it appear to the user that they are configuring the "SPI Controller", when in fact, they are really just selecting from one of several possible implementations.
Even if the "user" is you, it can make creating designs for target boards easier.
The main thing you want to do is create a dummy setup with a couple of boards from a couple of vendors and see if you can get it working, eg., have a blinking LEDs design built using vendor IP blocks, eg., an Altera LPM counter in the Altera design, and see if you can implement an identical Xilinx design, and all the associated infrastructure (generics on the parts, Tcl scripts for each tool, etc).
Cheers,
Dave
Honored Contributor
