Generate VHDL code from VHDL code

Its possible that you might be able to do this using a combination of Qsys _hw.tcl and generics.

Lets say I have a Qsys system that I can include or exclude an SPI device. That SPI device has an interface spi_selN, spi_clk, spi_mosi, and spi_miso.

Qsys will mangle the name slightly, lets say it adds the prefix spi_interface_XXX to all your signals. You could have a top-level like this:

generic (
    USE_SPI : boolean := true
    ...
g1: if (USE_SPI) generate
  -- Qsys system with SPI controller goes here
  ....
  -- Qsys SPI ports
  spi_interface_spi_selN => spi_selN,
  spi_interface_spi_clk   => spi_clk,
  spi_interface_spi_mosi => spi_mosi,
  ....
  ); -- end of Qsys ports
end generate;
g2: if (not USE_SPI) generate
  -- Qsys system without SPI controller goes here
  -- Unused SPI drivers
  spi_selN <= '1';
  spi_clk   <= '1';
  spi_mosi <= '1';
end generate;

You can then use a Tcl script to set the generic and generate the appropriate Qsys system.

Alternatively, you can use *exactly* the same Qsys system, and have the optional components interpret a generic that enables or disables them. That way those pins will exist on the Qsys component, but if they are not in use, then they will just drive deasserted levels ... just like the example here, but that logic would be inside each of your Qsys components.

Cheers,

Dave