Generate VHDL code from VHDL code

I've done a little reading in my book, but the chapter Configurations gives me a lot less information about how to use it than you did. I will still look through my book to see if I can find something usefull, but I didn't find what I was looking for yet unfortunately:(

I've also thought some more about what my program should look like. And it seems like Iv'e got some components I can bind together because they indeed always have the same in and outputs. So the only thing I would need to change is the entity name, since that will get the right architecture also. One problem fixable.

But than comes trouble, I also have components with inputs and outputs I can't specify yet so I can't make the signals for that either. If I would use the package option, I am still not able to do such things right? I can't make a "component a port();" and than hope all those in and outputs will be some magical way connected to the right signals in the toplevel, right?

Than I also have some components where some in and outputs must be present and others are extra, I thought that would be fixable in the same way as my problem above, or maybe even easier. But I wouldn't know how, maybe I need to look some more into the packages option.