Generate VHDL code from VHDL code

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Thanks for the great explanations.

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You're welcome.

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I indeed had the intention to get and read/search my VHDL book, but I keep forgetting about it. This week I must take that book and go and read it, after that maybe I'll have more or other questions and might be able to draw a bigger picture of what I want to do and how that might be possible. I think I at least have an idea where to search for, what to read and what to specify.

So for now it will be best to go and read that book and don't ask any questions anymore before I have done that.

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While you read your book, make sure to write code, and compile it using Modelsim and Quartus. That will help in understanding the code, and will ensure the code is valid (I have good books - good explanations, with bad code).

Cheers,

Dave