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So ive read and done(some parts of) the tutorial but I didn't quite get how it is all connected to each other or not. I can see 3 different boards and a map called share. I is correct you have to build the quartus or the spoc system only once and after that just change the tcl scripts to change something? But every board has its own tcl scripts, so you would have to write a tcl script for every kind of board you want to use? Or am I not getting the idea of the files at all?
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Each board has its own folder containing a top-level design file. The same SOPC system is used in each design, however, the XML description is re-processed for each project. This allows Quartus to create whatever hardware is specific to a particular FPGA architecture. For example, each FPGA has memory, but the memory can be different between architectures, so you need to process the SOPC file on a per board basis.
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I have been examining example 3 of the thread. As far as I understand the configurations examples, it seems like you would have to use a same kind of component again and again to give the configuration VHDL file any value.
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You need to pick up a VHDL book and look at what configurations are. A configuration can be used to map an 'entity' to a 'component'. If the port names on the entity and component are identical, then the mapping is trivial. If the two components are similar, but have different ports, then you can map which port connects to what. I'm not saying that these are the solution to your problem, I'm just suggesting that they might be. If you're getting confused by all the options, just skip it.
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So this way I wouldnt be able to change my component C from an SPI ip block to a RAM ip block for example, since than those in and outputs don't make sense anymore. Or is there some way to make this happen too with configurations, or would I have to declare in that file every kind of ip component I want to use?
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As I said above. If your SOPC/Qsys system has the same I/O then you do not need to change anything. As soon as you change the I/O, then you have different components, so naturally you need to have different instantiations of the components. However, in that case you can use a generic.
For example,
entity top_level is
generic (
DEVICE : integer := 0
);
port (
rstN : in std_logic;
clk : in std_logic;
pin_in : in std_logic_vector(7 downto 0);
pin_out : out std_logic(7 downto 0)
);
component a is
port (
rstN : in std_logic;
clk : in std_logic;
a_in : in std_logic;
a_out : out std_logic
);
component b
port (
rstN : in std_logic;
clk : in std_logic;
b_in : in std_logic_vector(1 downto 0);
b_out : out std_logic_vector(1 downto 0)
);
g1: if (DEVICE = 0) generate
u1: a
port map (
rstN => rstN,
clk => clk,
a_in => pin_in(0),
a_out => pin_out(0)
);
pin_out(7 downto 1) <= (others => '0');
end generate;
g2: if (DEVICE = 1) generate
u1: b
port map (
rstN => rstN,
clk => clk,
b_in => pin_in(1 downto 0),
b_out => pin_out(1 downto 0)
);
pin_out(7 downto 2) <= (others => '0');
end generate;
Note how this design has a common top-level, and two separate possible implementations, with the implementation selected by a generic.
Perhaps this will give you some idea ...
Cheers,
Dave
Honored Contributor
