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Altera_Forum
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12 years ago

Generate VHDL code from VHDL code

Hello, I have been wondering for a while if it is possible to let some standard tool (like quartus, or ISE or maybe even a windows tool) generate a VHDL file from previous written VHDL code. For...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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It is possible to import a pinmapping right?

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Sure, but there still has to be a one-to-one mapping between the pin names in your top-level HDL entity and your pin mapping script or spreadsheet. If you look at the tutorial source, you will see that correspondence, i.e., a top-level HDL file and a Tcl script with pin constraints, where those constraints use the same name as the top-level HDL. If your top-level HDL is generated by Qsys, then the top-level pin names change depending on how you name the components in the system.

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Than I would think the problem with not knowing how to put the signals together would be over, or am I thinking about this a little too easy? Let's say at least the inputs and outputs from the top-level are always the same, but only the signals vary with different components. I always have a component of type A, this component also always has the same in and outputs for every different component (so it only differs in architecture). And I also always have a component of type B, same inputs and outputs for every different component again.

Now I always want to connect a (yet undefined) component of type C, to a component of type A. And a (yet undefined) component of type D also connects to type A and B.

So we've got: C<>A<>D<>B Always

Is it than still not possible to say: ok since we have type A we need to connect it with type C and we need to do it this way: input Ax <= output Cx, input Ay <= output Cy

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This problem can be solved using VHDL configurations.

In VHDL a 'component' definition tells the compiler what pins a component has. Using a configuration you can map an entity to a component.

In your code, you can write the code to include known components A and B, and connect them to 'component' definitions for C and D. Then you use a configuration to map C and D to their implementations.

I posted a VHDL configurations example in this thread:

http://www.alteraforum.com/forum/showthread.php?t=30414&page=2

Take a look at VHDL configurations and let me know if they meet your requirements. If they don't, we can discuss using generate statements, generics, and Tcl.

Cheers,

Dave