Generate VHDL code from VHDL code

Thanks for the extensive explanation Dave.

It is possible to import a pinmapping right?

Than I would think the problem with not knowing how to put the signals together would be over, or am I thinkiing about this a little too easy?

Let's say at least the inputs and outputs from the toplevel are always the same, but only the signalls vary with different components. I always have a component of type A, this component also always has the same in and outputs for every different component(so it only differs in architecture). And I also always have a component of type B, same inputs and outputs for every different component again.

Now I always want to connect a (yet undifined)component of type C, to a component of type A. And a (yet undifined)component of type D also connects to type A and B.

So we've got: C<>A<>D<>B Always

Is it than still not possible to say: ok since we have type A we need to connect it with type C and we need to do it this way: input Ax <= output Cx, input Ay <= output Cy

I am also reading the tutorial, so maybe I will get those answers there too