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Altera_Forum
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12 years ago

Generate VHDL code from VHDL code

Hello, I have been wondering for a while if it is possible to let some standard tool (like quartus, or ISE or maybe even a windows tool) generate a VHDL file from previous written VHDL code. For...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I see I wasn't very clear.

The problem is that one way or another, this toplevel is going to be generated automatically. If there is no tool to do such a thing, it would become a self written program that would read all the inputs and outputs from the components and than decide how these things are going to be connected.

In some way it seems like an impossible thing to do, since it needs to be really general. Thats why I hoped there would be some kind of tool to do such a thing.

So that I dont have to write 20 different toplevels, for all the different designs I want to make(designs that might only differ one component for example).

I'm not sure if you could ''speak'' to qsys via TCL?

I try my best to make it less general, but it isn't as easy as i thought.