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Altera_Forum's avatar
Altera_Forum
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13 years ago

Generate in vhdl declaration

Hi, I have a single vhdl package that I would like to use for two projects. The constants in the two projects have the same name but different values. Can I use generate statement in the declarati...
Altera_Forum's avatar
Altera_Forum
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13 years ago

What you can do is use a separate package VHDL file for each project, but use the same package name.

This is how I do it when I have FPGA designs that just use different configuration settings but are based on the same VHDL code.