Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Generate in vhdl declaration

Hi, I have a single vhdl package that I would like to use for two projects. The constants in the two projects have the same name but different values. Can I use generate statement in the declarati...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

you cannot use generate inside a package. And you also cannot set a constant inside a generate if it is declared outside the generate.

But you can use a function: 


function set_ty return positive is
begin
  if proj = XX then
    return 6;
  elsif proj = YY then
     return 7;
   ..... etc
end function set_TY;
constant TY : positive := set_TY;