generate clock after a specific number

my code is:

entity test_out is
generic (period: time :=100ps;
halfperiod: time := 50ps);
port ( rit: in integer range 0 to 255; --delay for start clock
localCLK: inout std_logic 
) ;
end test_out;
architecture beha of test_out is
signal clock: std_logic;    --used to recycle the process
signal uscita: integer range 0 to 255:=0;
begin
clock<='0','1' after halfperiod;
    process(clock)
    begin
        if (clock='1')then
        clock<= '0' after halfperiod;
        else clock <='1' after halfperiod;
        end if;
            case (rit) is
                    when 0 => uscita<=0;
                    when 1 to 10 => uscita<=1 after 1ps;
                    when 11 to 20 => uscita<=2 after 10ps;    
                    when 21 to 30 => uscita<=3 after 20ps;    
                    when 31 to 40 => uscita<=4 after 30ps;    
                    when 41 to 50 => uscita<=5 after 40ps;
                    when 51 to 60 => uscita<=6 after 50ps;    
                    when 61 to 255 => uscita<=7 after 60ps;    
            end case;
            
            case(uscita) is
                    when 0 to 255=> localCLK <='1', '0' after halfperiod;
            end case;    
    end process;
end architecture;