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Altera_Forum
Honored Contributor
Honored ContributorGenerate Case Instantiation
Hi, I would like to instantiate a parameterized sub-module "test1" based on an input value SW[6:0]. So I implement a generate case structure as follows: always @(*) begin generate c...
Altera_ForumHonored Contributor
Honored ContributorI believe you need to learn how to design hardware first, then learn how to describe that hardware in Verilog. You can design hardware that dynamically responds to certain inputs in a specific way, but you can not change the specification dynamically - that is static.
