Generate Case Instantiation

I have tried to remove the always block, and it shows the same error messages. I guess the reason that causes this is SW[6:0] is a variable not a constant expression. So I guess it cannot pass the static elaboration? What I am interested to know is that is there a way to instantiate the same module with different set of parameters based on an input register value. As I showed in the above example, when the input register value is 7'b0, I will parameterize NUM_PULSE TO be 1 and SAMPLES_PER_CYCLE to be 8, while the input register value is 7'b1, I will parameterize NUM_PULSE TO be 1 and SAMPLES_PER_CYCLE to be 16, etc. I would really appreciate your guidance on this if you have a solution.