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I have synchronized my external reset signal through three DFF's a while back. This solved some other sporadic problems.
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If your design actually has something needing that reset to be synchronized (seems to be the case since some problems went away when you synchronized it), then you definitely need to use recovery/removal analysis. An example is a state machine that could have more than one state bit toggle at the exit from the reset state. It is critical that each potentially toggling state bit see the reset deassertion in the same clock cycle. Synchronizing the reset as you did is necessary. It is also necessary to do the timing analysis to make sure the synchronized reset is stable from the recovery time before the clock edge (like a tsu) until the removal time after the clock edge (like th) right at the register inputs.
If you have more than one clock domain with registers needing recovery/removal analysis, then the reset needs to be synchronized to each of those domains separately.
If you find that you have recovery/removal violations for a reset using global routing, then try making the reset nonglobal. Even a large fan-out using nonglobal routing can be faster than the large global buffer insertion delay.
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I meant by "large timing margin" that the external setup and hold timings are ok as measured by my Logic Analyzer.
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If you have used only a logic analyzer and not a scope, check signal integrity at the input pins with a scope. Also check the power pins for dropouts or other noise.
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One warning i get is that i'm using regular output pins as clock outputs to an external FIFO (60 MHz) and to SDRAM (120 MHz). The warning talks about jitter. I have several ns margin on both tsu/th so i can't see how this could cause problems (especially 20% of the times run on the same board).
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To minimize jitter, it is best to use a clock output pin that the PLL can drive with a direct connection. The device handbook documents which pins go with which PLLs.
An example where this would matter is an external DDR memory with a clock input that cannot tolerate the jitter potentially added by routing from the PLL to the output pin using anything other than the direct connection.
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