General timing constraints workflow?

Thanks Brad. I have synchronized my external reset signal through three DFF's a while back. This solved some other sporadic problems. I don't have any other asynchronous inputs and the design assistant flags no problems. I meant by "large timing margin" that the external setup and hold timings are ok as measured by my Logic Analyzer. Internal input setup and hold also looks ok as reported to my LA via the LAI. Still, the design occasional gets the hickups.

One warning i get is that i'm using regular output pins as clock outputs to an external FIFO (60 MHz) and to SDRAM (120 MHz). The warning talks about jitter. I have several ns margin on both tsu/th so i can't see how this could cause problems (especially 20% of the times run on the same board).

I have to dig into this step by step - first constraining (and understanding) the timings fully.

Thanks,

/John.