General timing constraints workflow?

To be completely honest, I would recommend that you transition to the Timequest analyzer. You will spend a few days going through the learning curve but after that, you have much more power to constrain the timing of your design.

Spending time learning the Classic timing analyzer at this point would not be the best use of your time. The classic timing analyzer is not supported for Cyclone III, Stratix III and newer parts.

However, to answer some of your questions.

1) The classic timing analyzer will automatically determine the clock frequencies of any clocks driven by PLL's in your design. The analyzer is smart enough to determine what logic uses what clock and will automatically perform setup and hold analysis for all internal nodes pertaining to that clock.

For any clocks that are driven directly from a top-level pin. You must specify the frequency of the clock in the project's timing settings.

2) You use the assignment editor to provide Input Delay, Output Delay, or tSU, tH, tPD, and tCO constraints for all user I/O.

3) Refer to http://www.altera.com/support/software/timing/sof-qts-timing.html (http://www.altera.com/support/software/timing/sof-qts-timing.html)

Really, I know it seems like it's not worth the time but you'll be more satisfied and have higher confidence in your design if you take the time to learn TimeQuest.

Jake