Honored Contributor
Honored ContributorBy digging deeper into the base clock connections, I see some kind of slave registers on a 16bit bus with a rd and wr line . I suspect this might be the interface to the EPCS device, since it has to be able to read this device before any of the fpga is configured (ie base clock driven logic), but also have r/w access after configuration (via nios/avalon bus).
There isn't any explicit connection to the base clock in any of the design, but since it is an optional component it must use some configurable logic rather than just dedicated hard cells.
