--- Quote Start ---
Hi, I'm having some issues with my gate level sim not matching my RTL. I need a gate level sim to gather some toggle rates for power estimation.
The gate level netlist (.vho) is generated from Altera Quartus II software and I plug in the gate level netlist in place of the DUT and keep the same testbench. However the sim results were totally different. Most of the nodes are not toggling at all(seem to be in reset or inhibit state). Anyone with ideas or suggestion? It will be much appreciated..been stuck on this for a while now.
I have tried the sim without the timing file (.sdo) and add +notimingcheck on the ModelSim command VSIM but had no luck.
--- Quote End ---
Hi,
maybe your problem is not simulation related. Did you check your Quartus messages ?
Maybe the synthesis tool has some parts of your design removed. Look for things like output stuck a gnd or vcc .
Kind regards
Gerd
Honored Contributor
