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Altera_Forum's avatar
Altera_Forum
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9 years ago

Gated clocks

Hi folks. I have noticed in an Altera help page that gated clocks are not recommended:

-----> http://quartushelp.altera.com/15.1/index.htm#reference/glossary/def_gatedclk.htm

In another page, Altera provides guidelines for implementing a gated clock:

-----> http://quartushelp.altera.com/15.1/index.htm#verify/da/comp_file_rules_clock.htm

It seems convenient to do this for generating a SPI clock, for example, using the chip select signal as a clock enable. Is there a better alternative? Here are my code and resulting RTL snapshot for reference.

This example incorporates both methods outlined in the help page.

Any comments greatly appreciated! 


clock_enable_n : process(clk, reset_n)
begin
  if (reset_n = '0') then
    clk_enable_n    <= '0';
  elsif rising_edge(clk) then
    clk_enable_n    <= clock_en_n;
  end if;
end process clock_enable_n;
clock_out_n    <= clk or clk_enable_n;
clock_enable : process(clk, reset_n)
begin
  if (reset_n = '0') then
    clk_enable      <= '0';
  elsif falling_edge(clk) then
    clk_enable      <= not(clock_en_n);
  end if;
end process clock_enable;
clock_out  <= clk and clk_enable;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    The advice on gated clocks is meant for internal fpga design. If you are sending clock out then you can do that directly provided it has correct alignment to your data.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi,

    as Altera's note mentions, you'll get some "clock skew and internal hold violations", because your clock is not routed through the FPGA's balanced clock distribution network, but has to go through the logic fabric.

    I'm using SPI masters and SPI slaves in my design which treat the MISO/MOSI signals as asynchronous signals, and synchronizes them (two registers), which means that the clock uncertainty doesn't matter. And yes, it works perfectly. As long as the SPI clock is so slow that the MISO/MOSI signals are settled until you sample them, and as long as the expected clock jitter (picoseconds maybe) does not violate the timing requirements of the other SPI side. This applies for most SPI applications, e.g. when you have a 1 MBit/s SPI bus (for any off-the-shelf SPI chip), and use a 100 MHz FPGA clock (not exactly uncommon).

    If you want to use a synchronous SPI master/slave (which is inevitable if you need really high performance), things change. As kaz said, you must ensure proper clock/data alignment. This means you should constrain your CS/MISO/MOSI signals in TimeQuest as synchronous inputs/outputs, and SCK as a clock input/aoutput. I am not 100% sure about this, but I think that TimeQuest is able to determine the worst-case skew introduced by that clock gating circuit when you do so.

    Best regards,

    GooGooCluster
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    altough your circuit would not be logically incorrect, it is not advisable to use gated clocks as these would give rise to 'dangerous' delays. In larger designs this may cause problems. Personally i prefer to utilize morre logic gates and keep the whole system synchronous rather then gating the clock.