Gated clocks

Hi,

as Altera's note mentions, you'll get some "clock skew and internal hold violations", because your clock is not routed through the FPGA's balanced clock distribution network, but has to go through the logic fabric.

I'm using SPI masters and SPI slaves in my design which treat the MISO/MOSI signals as asynchronous signals, and synchronizes them (two registers), which means that the clock uncertainty doesn't matter. And yes, it works perfectly. As long as the SPI clock is so slow that the MISO/MOSI signals are settled until you sample them, and as long as the expected clock jitter (picoseconds maybe) does not violate the timing requirements of the other SPI side. This applies for most SPI applications, e.g. when you have a 1 MBit/s SPI bus (for any off-the-shelf SPI chip), and use a 100 MHz FPGA clock (not exactly uncommon).

If you want to use a synchronous SPI master/slave (which is inevitable if you need really high performance), things change. As kaz said, you must ensure proper clock/data alignment. This means you should constrain your CS/MISO/MOSI signals in TimeQuest as synchronous inputs/outputs, and SCK as a clock input/aoutput. I am not 100% sure about this, but I think that TimeQuest is able to determine the worst-case skew introduced by that clock gating circuit when you do so.

Best regards,

GooGooCluster