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Altera_Forum's avatar
Altera_Forum
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16 years ago

gated clock

I have a 100 Mhz clock coming to my FPGA CLOCK100. This goes to the SOPC which has a PLL. The PLL generates a 150 MHz clock CLOCK150 which goes to my custom logic which has a PLL. The output of the P...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I would typically use the lock output of the PLL to control the reset logic in my design.

Jake