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Altera_Forum
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18 years ago

gated and muxed clocks with classic timing analyzer

For diagnostic purposes we have added gated and muxed clocks to our fpga design. The gated clock is the inverse of the input clock. The muxed clock logic switches the output clock to the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

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You may want to assign inv_clk_en with the Not a Clock assignment, so it gets ignored.

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That assignment works only if inv_clk_en is an input pin. The last time I looked at that assignment, it was not available for internal signals.

Always be careful when driving clocks with internal logic even if there are no reported timing violations. See my posts at http://www.alteraforum.com/forum/showthread.php?t=754.