gated and muxed clocks with classic timing analyzer

Since you're doing it with gates, it gets more complicated, because you are introducing clock skew. I assume when you switch what drives the clock, you don't care what happens? For example, if you drive out clk_in, and less than a half cycle later you drive out ~clk_in, then you would have a transfer from clk_in to ~clk_in, which means you're requirement is half the period of clk_in.

You can put an absolute clock on the ouput of the mux. That works nicely as it ignores all the logic leading up to the that point, so there is no gating, not multiple clocks, etc. But it's bad in that it ignores this extra delay, so interfaces to other domains(or I/O) won't account for this extra delay.

You may want to assign inv_clk_en with the Not a Clock assignment, so it gets ignored.

Just some ideas to get you started. TimeQuest is generally much better equipped for this, although it is generally doable with the Classic Timing Analyzer.