Gate level simulation

Hi:

I use modelsim se 6.5c to do gate-level simulation. I've done the RTL simulaiton before and it functions well. But for the GL simulation. An error occur:

Error: (vsim-3601) Iteration limit reached at time 0 ps.

I surfed the internet. Some said it was caused by the number of loop larger than the iteration limit and I should increase the interation limt. So I did. But the error remains.

Besides, there is a warning saying " Invalid transition to 'X' detected on PLL input clk. This edge will be ignored. Time: 0 Instance: top_vlg_vec_tst.i1.clkgen_inst.ClkConv.altpll_component.pll.n1" Can this cause the error? And I really don't find "X" transition on PLL input clk in my code.

Please help me. I have a deadline. Thank you very much.