Gate level simulation using Nc-verilog

Hello ,

I am facing problem when i tried to simulate netlist with SDO file . I generated

netlist using quartus 2 7.2 version, stratix device. If do not include SDO file , it is simulatng , but when i include SDO file , the following error is reported :

-- (delayfile

|

ncvlog: *e,expmpa (..//pwmtop_v.sdo,23|0): expecting the keyword 'module', 'macromodule' or 'primitive'[a.1].

(`include file: ..//pwmtop_v.sdo line 23, file)

I have included Stratix_atoms.v also. It is compiling .

Kindly help me.