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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

To change clocking to clock 40MHz and clock enable you need to add to every clock edge assignment:

if (rising_edge(clk40mhz) then

if clken = '1' then -- your 100KHz rate

...etc

You must make sure timing is right before we blame the filtering itself.

I don't think you will need multicycle as 40MHz is too slow anyway