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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ok, i will try to do that. Do u think SLOW MODEL clock setup failure is due to this gated clock? And the filter failing on board as wel?

(The filter works fine in gate level simulation).

Please advice.