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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I believe you should not use the enable as clock since it is gated clock and needs extra care. You can use the 40MHz to clock your registers then use that enable as clock enable. 40MHz is no problem to achieve.